Improving Transactional Code Generation via Variable Annotation and Barrier Elision
Autor(a) principal: | |
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Data de Publicação: | 2020 |
Outros Autores: | , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1109/IPDPS47924.2020.00107 http://hdl.handle.net/11449/199200 |
Resumo: | With chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application tool rather than just an interesting research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently available, the GNU Compiler Collection (GCC), does not generate code that achieves desirable performance. This paper presents a detailed analysis of transactional code generated by GCC and by a proposed transactional memory support added to the Clang/LLVM compiler framework. Experimental results support the following contributions: (a) STM's performance overhead is due to an excessive amount of read and write barriers added by the compiler; (b) a new annotation mechanism for the Clang/LLVM compiler framework that aims to overcome the barrier over-instrumentation problem by allowing programmers to specify which variables should be free from transactional instrumentation; (c) a profiling tool that ranks the most accessed memory locations at runtime, working as a guiding tool for programmers to annotate the code. Furthermore, it is revealed that, by correctly using the annotations on just a few lines of code, it is possible to reduce the total number of instrumented barriers by 95% and to achieve speed-ups of up to 7× when compared to the original code generated by GCC and the Clang compiler. |
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Improving Transactional Code Generation via Variable Annotation and Barrier ElisionCompilersDebuggingTransactional MemoryWith chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application tool rather than just an interesting research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently available, the GNU Compiler Collection (GCC), does not generate code that achieves desirable performance. This paper presents a detailed analysis of transactional code generated by GCC and by a proposed transactional memory support added to the Clang/LLVM compiler framework. Experimental results support the following contributions: (a) STM's performance overhead is due to an excessive amount of read and write barriers added by the compiler; (b) a new annotation mechanism for the Clang/LLVM compiler framework that aims to overcome the barrier over-instrumentation problem by allowing programmers to specify which variables should be free from transactional instrumentation; (c) a profiling tool that ranks the most accessed memory locations at runtime, working as a guiding tool for programmers to annotate the code. Furthermore, it is revealed that, by correctly using the annotations on just a few lines of code, it is possible to reduce the total number of instrumented barriers by 95% and to achieve speed-ups of up to 7× when compared to the original code generated by GCC and the Clang compiler.Institute of Computing-UNICAMPUNESP-Univ Estadual PaulistaUNESP-Univ Estadual PaulistaUniversidade Estadual de Campinas (UNICAMP)Universidade Estadual Paulista (Unesp)De Carvalho, Joao P. L.Honorio, Bruno C.Baldassin, Alexandra [UNESP]Araujo, Guido2020-12-12T01:33:29Z2020-12-12T01:33:29Z2020-05-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject1008-1017http://dx.doi.org/10.1109/IPDPS47924.2020.00107Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020, p. 1008-1017.http://hdl.handle.net/11449/19920010.1109/IPDPS47924.2020.001072-s2.0-85088903450Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020info:eu-repo/semantics/openAccess2021-10-23T04:45:40Zoai:repositorio.unesp.br:11449/199200Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T15:31:43.078215Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
title |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
spellingShingle |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision De Carvalho, Joao P. L. Compilers Debugging Transactional Memory |
title_short |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
title_full |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
title_fullStr |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
title_full_unstemmed |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
title_sort |
Improving Transactional Code Generation via Variable Annotation and Barrier Elision |
author |
De Carvalho, Joao P. L. |
author_facet |
De Carvalho, Joao P. L. Honorio, Bruno C. Baldassin, Alexandra [UNESP] Araujo, Guido |
author_role |
author |
author2 |
Honorio, Bruno C. Baldassin, Alexandra [UNESP] Araujo, Guido |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual de Campinas (UNICAMP) Universidade Estadual Paulista (Unesp) |
dc.contributor.author.fl_str_mv |
De Carvalho, Joao P. L. Honorio, Bruno C. Baldassin, Alexandra [UNESP] Araujo, Guido |
dc.subject.por.fl_str_mv |
Compilers Debugging Transactional Memory |
topic |
Compilers Debugging Transactional Memory |
description |
With chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application tool rather than just an interesting research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently available, the GNU Compiler Collection (GCC), does not generate code that achieves desirable performance. This paper presents a detailed analysis of transactional code generated by GCC and by a proposed transactional memory support added to the Clang/LLVM compiler framework. Experimental results support the following contributions: (a) STM's performance overhead is due to an excessive amount of read and write barriers added by the compiler; (b) a new annotation mechanism for the Clang/LLVM compiler framework that aims to overcome the barrier over-instrumentation problem by allowing programmers to specify which variables should be free from transactional instrumentation; (c) a profiling tool that ranks the most accessed memory locations at runtime, working as a guiding tool for programmers to annotate the code. Furthermore, it is revealed that, by correctly using the annotations on just a few lines of code, it is possible to reduce the total number of instrumented barriers by 95% and to achieve speed-ups of up to 7× when compared to the original code generated by GCC and the Clang compiler. |
publishDate |
2020 |
dc.date.none.fl_str_mv |
2020-12-12T01:33:29Z 2020-12-12T01:33:29Z 2020-05-01 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1109/IPDPS47924.2020.00107 Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020, p. 1008-1017. http://hdl.handle.net/11449/199200 10.1109/IPDPS47924.2020.00107 2-s2.0-85088903450 |
url |
http://dx.doi.org/10.1109/IPDPS47924.2020.00107 http://hdl.handle.net/11449/199200 |
identifier_str_mv |
Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020, p. 1008-1017. 10.1109/IPDPS47924.2020.00107 2-s2.0-85088903450 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
1008-1017 |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128526754250752 |