On the efficiency of transactional code generation: A GCC case study

• Autor(a) principal: Honorio, Bruno Chinelato [UNESP]
• Data de Publicação: 2018
• Outros Autores: De Carvalho, Joao Paulo Labegalini, Baldassin, Alexandro Jose [UNESP]
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/WSCAD.2018.00037; http://hdl.handle.net/11449/190536
• topic: Compilers; Optimization; Over-instrumentation; Parallel programming; Transactional memory

Memory transactions are becoming more popular as chip manufacturers are building native support for their execution. Although current Intel and IBM microprocessors support transactions in their instruction set architectures, there is still room for improvement in the compiler and runtime front. The GNU Compiler Collection (GCC) has language support for transactions, although performance is still a hindrance for its wider use. In this paper we perform an up-to-date study of the GCC transactional code generation and highlight where the main performance losses are coming from. Our study indicates that one of the main source of inefficiency is the read and write barriers inserted by the compiler. Most of this instrumentation is required because the compiler cannot determine, at compile time, whether a region of memory will be accessed concurrently or not. To overcome those limitations, we propose new language constructs that allow programmers to specify which memory locations should be free from instrumentation. Initial experimental results show a good speedup when barriers are elided using our proposed language support compared to the original code generated by GCC.