Output conductance at saturation like region on Line-TFET for different dimensions

• Autor(a) principal: Goncalez Filho, Walter
• Data de Publicação: 2019
• Outros Autores: Martino, Joao A., Agopian, Paula G. D. [UNESP], IEEE
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://hdl.handle.net/11449/195388
• topic: Line TFET; output conductance; analog circuit design

This work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate area (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.