Efficient Realizations of CNOT gates in IBM's Quantum Computers

Detalhes bibliográficos
Autor(a) principal: De Almeida, Alexandre A. A. [UNESP]
Data de Publicação: 2018
Outros Autores: Dueck, Gerhard W., Da Silva, Alexandre C. R. [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/ISED.2018.8704098
http://hdl.handle.net/11449/228683
Resumo: IBM's quantum computers implement gates from Clifford +T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.
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spelling Efficient Realizations of CNOT gates in IBM's Quantum ComputersIBM's quantum computers implement gates from Clifford +T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Department of Electrical Engineering FEIS - Univ Estadual PaulistaFaculty of Computer Science University of New BrunswickDepartment of Electrical Engineering FEIS - Univ Estadual PaulistaCAPES: 309193/2015-0CNPq: 309193/2015-0Universidade Estadual Paulista (UNESP)University of New BrunswickDe Almeida, Alexandre A. A. [UNESP]Dueck, Gerhard W.Da Silva, Alexandre C. R. [UNESP]2022-04-29T08:28:04Z2022-04-29T08:28:04Z2018-07-02info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject58-62http://dx.doi.org/10.1109/ISED.2018.8704098Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018, p. 58-62.http://hdl.handle.net/11449/22868310.1109/ISED.2018.87040982-s2.0-85065963720Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018info:eu-repo/semantics/openAccess2024-07-04T19:11:39Zoai:repositorio.unesp.br:11449/228683Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T19:19:39.842840Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Efficient Realizations of CNOT gates in IBM's Quantum Computers
title Efficient Realizations of CNOT gates in IBM's Quantum Computers
spellingShingle Efficient Realizations of CNOT gates in IBM's Quantum Computers
De Almeida, Alexandre A. A. [UNESP]
title_short Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_full Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_fullStr Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_full_unstemmed Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_sort Efficient Realizations of CNOT gates in IBM's Quantum Computers
author De Almeida, Alexandre A. A. [UNESP]
author_facet De Almeida, Alexandre A. A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
author_role author
author2 Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (UNESP)
University of New Brunswick
dc.contributor.author.fl_str_mv De Almeida, Alexandre A. A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
description IBM's quantum computers implement gates from Clifford +T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.
publishDate 2018
dc.date.none.fl_str_mv 2018-07-02
2022-04-29T08:28:04Z
2022-04-29T08:28:04Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/ISED.2018.8704098
Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018, p. 58-62.
http://hdl.handle.net/11449/228683
10.1109/ISED.2018.8704098
2-s2.0-85065963720
url http://dx.doi.org/10.1109/ISED.2018.8704098
http://hdl.handle.net/11449/228683
identifier_str_mv Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018, p. 58-62.
10.1109/ISED.2018.8704098
2-s2.0-85065963720
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 58-62
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
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reponame_str Repositório Institucional da UNESP
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repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
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