Efficient Realizations of CNOT gates in IBM's Quantum Computers

Detalhes bibliográficos
Autor(a) principal: Almeida, Alexandre A. A. de [UNESP]
Data de Publicação: 2018
Outros Autores: Dueck, Gerhard W., Silva, Alexandre C. R. da [UNESP], Jose, B. A., Mathew, J.
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://hdl.handle.net/11449/185748
Resumo: IBM's quantum computers implement gates from Clifford+T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.
id UNSP_a3ea9ee9bfdd10d4cf44c4c2c12adc7e
oai_identifier_str oai:repositorio.unesp.br:11449/185748
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling Efficient Realizations of CNOT gates in IBM's Quantum ComputersIBM's quantum computers implement gates from Clifford+T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)NSERCFEIS Univ Estadual Paulista, Dept Elect Engn, Ilha Solteira, BrazilUniv New Brunswick, Fac Comp Sci, Fredericton, NB, CanadaFEIS Univ Estadual Paulista, Dept Elect Engn, Ilha Solteira, BrazilCNPq: 309193/2015-0CAPES: 001IeeeUniversidade Estadual Paulista (Unesp)Univ New BrunswickAlmeida, Alexandre A. A. de [UNESP]Dueck, Gerhard W.Silva, Alexandre C. R. da [UNESP]Jose, B. A.Mathew, J.2019-10-04T12:38:15Z2019-10-04T12:38:15Z2018-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject58-62Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018). New York: Ieee, p. 58-62, 2018.http://hdl.handle.net/11449/185748WOS:000469312100012Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018)info:eu-repo/semantics/openAccess2024-07-04T19:11:50Zoai:repositorio.unesp.br:11449/185748Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T22:02:28.760093Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Efficient Realizations of CNOT gates in IBM's Quantum Computers
title Efficient Realizations of CNOT gates in IBM's Quantum Computers
spellingShingle Efficient Realizations of CNOT gates in IBM's Quantum Computers
Almeida, Alexandre A. A. de [UNESP]
title_short Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_full Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_fullStr Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_full_unstemmed Efficient Realizations of CNOT gates in IBM's Quantum Computers
title_sort Efficient Realizations of CNOT gates in IBM's Quantum Computers
author Almeida, Alexandre A. A. de [UNESP]
author_facet Almeida, Alexandre A. A. de [UNESP]
Dueck, Gerhard W.
Silva, Alexandre C. R. da [UNESP]
Jose, B. A.
Mathew, J.
author_role author
author2 Dueck, Gerhard W.
Silva, Alexandre C. R. da [UNESP]
Jose, B. A.
Mathew, J.
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
Univ New Brunswick
dc.contributor.author.fl_str_mv Almeida, Alexandre A. A. de [UNESP]
Dueck, Gerhard W.
Silva, Alexandre C. R. da [UNESP]
Jose, B. A.
Mathew, J.
description IBM's quantum computers implement gates from Clifford+T gate library. All single qubit gates are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be achieved by a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. To show the potential of the proposed transformations, an example is presented where a reduction of 44% in the gate count and a 26% reduction in the number of levels for IBM's QX5 computer is achieved. An algorithm that is considered state of the art, is used for the comparison.
publishDate 2018
dc.date.none.fl_str_mv 2018-01-01
2019-10-04T12:38:15Z
2019-10-04T12:38:15Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018). New York: Ieee, p. 58-62, 2018.
http://hdl.handle.net/11449/185748
WOS:000469312100012
identifier_str_mv Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018). New York: Ieee, p. 58-62, 2018.
WOS:000469312100012
url http://hdl.handle.net/11449/185748
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings Of The 2018 8th International Symposium On Embedded Computing And System Design (ised 2018)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 58-62
dc.publisher.none.fl_str_mv Ieee
publisher.none.fl_str_mv Ieee
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808129385724641280