CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures

Detalhes bibliográficos
Autor(a) principal: De Almeida, Alexandre A. A. [UNESP]
Data de Publicação: 2019
Outros Autores: Dueck, Gerhard W., Da Silva, Alexandre C. R. [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/ISMVL.2019.00010
http://hdl.handle.net/11449/187875
Resumo: IBM architectures impose some restrictions the quantum circuits that can be implemented. Only gates from Clifford+T gate library can be used and not all of the CNOT gates are available. Some of the CNOT need to be mapped into a sequence of gates. In this paper we present a set of mappings to conform to the restrictions imposed by IBM's architectures. These mappings require fewer gates than SWAP gates. It is well known, that permuting the qubits will yield circuits with different number of gates. The design in this paper uses efficient mappings with qubit permutations to obtain circuits with a reduced number of gates. Results have shown that the proposed approach reduces circuits by up to 64% compared with Qiskit and up to 42% compared with another mapping algorithm.
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spelling CNOT Gate Mappings to Clifford+T Circuits in IBM ArchitecturesClifford+T circuitsCNOT mappingIBM architecturesIBM architectures impose some restrictions the quantum circuits that can be implemented. Only gates from Clifford+T gate library can be used and not all of the CNOT gates are available. Some of the CNOT need to be mapped into a sequence of gates. In this paper we present a set of mappings to conform to the restrictions imposed by IBM's architectures. These mappings require fewer gates than SWAP gates. It is well known, that permuting the qubits will yield circuits with different number of gates. The design in this paper uses efficient mappings with qubit permutations to obtain circuits with a reduced number of gates. Results have shown that the proposed approach reduces circuits by up to 64% compared with Qiskit and up to 42% compared with another mapping algorithm.School of Engineering Ilha Solteira São Paulo State University (Unesp)Faculty of Computer Science University of New BrunswickSchool of Engineering Ilha Solteira São Paulo State University (Unesp)Universidade Estadual Paulista (Unesp)University of New BrunswickDe Almeida, Alexandre A. A. [UNESP]Dueck, Gerhard W.Da Silva, Alexandre C. R. [UNESP]2019-10-06T15:49:57Z2019-10-06T15:49:57Z2019-05-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject7-12http://dx.doi.org/10.1109/ISMVL.2019.00010Proceedings of The International Symposium on Multiple-Valued Logic, v. 2019-May, p. 7-12.0195-623Xhttp://hdl.handle.net/11449/18787510.1109/ISMVL.2019.000102-s2.0-85069157971Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings of The International Symposium on Multiple-Valued Logicinfo:eu-repo/semantics/openAccess2021-10-23T16:30:41Zoai:repositorio.unesp.br:11449/187875Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T18:59:05.886172Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
title CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
spellingShingle CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
De Almeida, Alexandre A. A. [UNESP]
Clifford+T circuits
CNOT mapping
IBM architectures
title_short CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
title_full CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
title_fullStr CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
title_full_unstemmed CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
title_sort CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
author De Almeida, Alexandre A. A. [UNESP]
author_facet De Almeida, Alexandre A. A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
author_role author
author2 Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
author2_role author
author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
University of New Brunswick
dc.contributor.author.fl_str_mv De Almeida, Alexandre A. A. [UNESP]
Dueck, Gerhard W.
Da Silva, Alexandre C. R. [UNESP]
dc.subject.por.fl_str_mv Clifford+T circuits
CNOT mapping
IBM architectures
topic Clifford+T circuits
CNOT mapping
IBM architectures
description IBM architectures impose some restrictions the quantum circuits that can be implemented. Only gates from Clifford+T gate library can be used and not all of the CNOT gates are available. Some of the CNOT need to be mapped into a sequence of gates. In this paper we present a set of mappings to conform to the restrictions imposed by IBM's architectures. These mappings require fewer gates than SWAP gates. It is well known, that permuting the qubits will yield circuits with different number of gates. The design in this paper uses efficient mappings with qubit permutations to obtain circuits with a reduced number of gates. Results have shown that the proposed approach reduces circuits by up to 64% compared with Qiskit and up to 42% compared with another mapping algorithm.
publishDate 2019
dc.date.none.fl_str_mv 2019-10-06T15:49:57Z
2019-10-06T15:49:57Z
2019-05-01
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/ISMVL.2019.00010
Proceedings of The International Symposium on Multiple-Valued Logic, v. 2019-May, p. 7-12.
0195-623X
http://hdl.handle.net/11449/187875
10.1109/ISMVL.2019.00010
2-s2.0-85069157971
url http://dx.doi.org/10.1109/ISMVL.2019.00010
http://hdl.handle.net/11449/187875
identifier_str_mv Proceedings of The International Symposium on Multiple-Valued Logic, v. 2019-May, p. 7-12.
0195-623X
10.1109/ISMVL.2019.00010
2-s2.0-85069157971
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Proceedings of The International Symposium on Multiple-Valued Logic
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 7-12
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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