An accurate low-voltage analog memory-cell with built-in multiplication

• Autor(a) principal: De Lima, J. A. [UNESP]
• Data de Publicação: 2001
• Outros Autores: Cordeiro, A. S. [UNESP]
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/ISCAS.2001.921798; http://hdl.handle.net/11449/66423
• topic: Analog storage; Buffer storage; Computer simulation; Gates (transistor); Learning algorithms; Printed circuit design; Transconductance; Analog memory cells; CMOS integrated circuits

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.