Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's
Autor(a) principal: | |
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Data de Publicação: | 2022 |
Outros Autores: | , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1109/SBMICRO55822.2022.9881005 http://hdl.handle.net/11449/246006 |
Resumo: | This paper analyzes the influence of uniaxially strained silicon on two-stage operational transconductance amplifiers (OTA) designed with SOI FinFETs. The OTA is designed with unstrained and strained SOI FinFETs. The circuit design was performed using experimental FinFETs data through LookUp Table (LUT) and Verilog-A model. Two different strategies were evaluated for designing the OTA: the same current bias (Iss) and the same inversion condition (gm/IDS), In both strained designs, the mobility improvement thanks to mechanical stress is responsible for higher voltage gain and gain-bandwidth product. Between the strained designs, the one that consider the same current bias of the unstrained one presents a lower power consumption due to the lower drain current compared to the same inversion condition. In summary, the OTA performance increase when it is designed with strained FinFET's. |
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Repositório Institucional da UNESP |
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Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET'sFinFETMechanical StrainOperational Transconductance AmplifiersThis paper analyzes the influence of uniaxially strained silicon on two-stage operational transconductance amplifiers (OTA) designed with SOI FinFETs. The OTA is designed with unstrained and strained SOI FinFETs. The circuit design was performed using experimental FinFETs data through LookUp Table (LUT) and Verilog-A model. Two different strategies were evaluated for designing the OTA: the same current bias (Iss) and the same inversion condition (gm/IDS), In both strained designs, the mobility improvement thanks to mechanical stress is responsible for higher voltage gain and gain-bandwidth product. Between the strained designs, the one that consider the same current bias of the unstrained one presents a lower power consumption due to the lower drain current compared to the same inversion condition. In summary, the OTA performance increase when it is designed with strained FinFET's.UNESP Sao Paulo State UniversityLSI/PSI/USP University of Sao PauloUNESP Sao Paulo State UniversityUniversidade Estadual Paulista (UNESP)Universidade de São Paulo (USP)Ribeiro, Arllen D. R. [UNESP]Araujo, Gustavo V.Martino, Joao A.Agopian, Paula G. D. [UNESP]2023-07-29T12:29:12Z2023-07-29T12:29:12Z2022-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1109/SBMICRO55822.2022.988100536th Symposium on Microelectronics Technology, SBMICRO 2022 - Proceedings.http://hdl.handle.net/11449/24600610.1109/SBMICRO55822.2022.98810052-s2.0-85139208971Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng36th Symposium on Microelectronics Technology, SBMICRO 2022 - Proceedingsinfo:eu-repo/semantics/openAccess2023-07-29T12:29:12Zoai:repositorio.unesp.br:11449/246006Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T18:09:00.754776Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
title |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
spellingShingle |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's Ribeiro, Arllen D. R. [UNESP] FinFET Mechanical Strain Operational Transconductance Amplifiers |
title_short |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
title_full |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
title_fullStr |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
title_full_unstemmed |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
title_sort |
Uniaxially strained silicon influence on Two-stage Operational Transconductance Amplifiers designed with SOI FinFET's |
author |
Ribeiro, Arllen D. R. [UNESP] |
author_facet |
Ribeiro, Arllen D. R. [UNESP] Araujo, Gustavo V. Martino, Joao A. Agopian, Paula G. D. [UNESP] |
author_role |
author |
author2 |
Araujo, Gustavo V. Martino, Joao A. Agopian, Paula G. D. [UNESP] |
author2_role |
author author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (UNESP) Universidade de São Paulo (USP) |
dc.contributor.author.fl_str_mv |
Ribeiro, Arllen D. R. [UNESP] Araujo, Gustavo V. Martino, Joao A. Agopian, Paula G. D. [UNESP] |
dc.subject.por.fl_str_mv |
FinFET Mechanical Strain Operational Transconductance Amplifiers |
topic |
FinFET Mechanical Strain Operational Transconductance Amplifiers |
description |
This paper analyzes the influence of uniaxially strained silicon on two-stage operational transconductance amplifiers (OTA) designed with SOI FinFETs. The OTA is designed with unstrained and strained SOI FinFETs. The circuit design was performed using experimental FinFETs data through LookUp Table (LUT) and Verilog-A model. Two different strategies were evaluated for designing the OTA: the same current bias (Iss) and the same inversion condition (gm/IDS), In both strained designs, the mobility improvement thanks to mechanical stress is responsible for higher voltage gain and gain-bandwidth product. Between the strained designs, the one that consider the same current bias of the unstrained one presents a lower power consumption due to the lower drain current compared to the same inversion condition. In summary, the OTA performance increase when it is designed with strained FinFET's. |
publishDate |
2022 |
dc.date.none.fl_str_mv |
2022-01-01 2023-07-29T12:29:12Z 2023-07-29T12:29:12Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1109/SBMICRO55822.2022.9881005 36th Symposium on Microelectronics Technology, SBMICRO 2022 - Proceedings. http://hdl.handle.net/11449/246006 10.1109/SBMICRO55822.2022.9881005 2-s2.0-85139208971 |
url |
http://dx.doi.org/10.1109/SBMICRO55822.2022.9881005 http://hdl.handle.net/11449/246006 |
identifier_str_mv |
36th Symposium on Microelectronics Technology, SBMICRO 2022 - Proceedings. 10.1109/SBMICRO55822.2022.9881005 2-s2.0-85139208971 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
36th Symposium on Microelectronics Technology, SBMICRO 2022 - Proceedings |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808128902483148800 |