Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width
Autor(a) principal: | |
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Data de Publicação: | 2016 |
Outros Autores: | , , , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/159329 |
Resumo: | We investigate for the first time the influence of the back gate bias (V-B) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative V-B the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure. |
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Repositório Institucional da UNESP |
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2946 |
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Back gate bias influence on SOI Omega-gate nanowire down to 10 nm widthSOIOmega-GateNanowireBack gateWe investigate for the first time the influence of the back gate bias (V-B) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative V-B the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Univ Sao Paulo, LSI PSI USP, Sao Paulo, BrazilUniv Estadual Paulista, UNESP, Sao Joao Da Boa Vista, BrazilCEA, LETI, Minatec Campus, F-38054 Grenoble, FranceUniv Grenoble Alpes, F-38054 Grenoble, FranceUniv Estadual Paulista, UNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)Universidade Estadual Paulista (Unesp)CEAUniv Grenoble AlpesAlmeida, L. M.Agopian, P. G. D. [UNESP]Martino, J. A.Barraud, S.Vinet, M.Faynot, O.IEEE2018-11-26T15:38:00Z2018-11-26T15:38:00Z2016-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject32016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016.http://hdl.handle.net/11449/159329WOS:00039269300002404969095954656960000-0002-0886-7798Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s)info:eu-repo/semantics/openAccess2021-10-23T21:47:05Zoai:repositorio.unesp.br:11449/159329Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T21:43:07.696685Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
title |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
spellingShingle |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width Almeida, L. M. SOI Omega-Gate Nanowire Back gate |
title_short |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
title_full |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
title_fullStr |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
title_full_unstemmed |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
title_sort |
Back gate bias influence on SOI Omega-gate nanowire down to 10 nm width |
author |
Almeida, L. M. |
author_facet |
Almeida, L. M. Agopian, P. G. D. [UNESP] Martino, J. A. Barraud, S. Vinet, M. Faynot, O. IEEE |
author_role |
author |
author2 |
Agopian, P. G. D. [UNESP] Martino, J. A. Barraud, S. Vinet, M. Faynot, O. IEEE |
author2_role |
author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) Universidade Estadual Paulista (Unesp) CEA Univ Grenoble Alpes |
dc.contributor.author.fl_str_mv |
Almeida, L. M. Agopian, P. G. D. [UNESP] Martino, J. A. Barraud, S. Vinet, M. Faynot, O. IEEE |
dc.subject.por.fl_str_mv |
SOI Omega-Gate Nanowire Back gate |
topic |
SOI Omega-Gate Nanowire Back gate |
description |
We investigate for the first time the influence of the back gate bias (V-B) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative V-B the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure. |
publishDate |
2016 |
dc.date.none.fl_str_mv |
2016-01-01 2018-11-26T15:38:00Z 2018-11-26T15:38:00Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016. http://hdl.handle.net/11449/159329 WOS:000392693000024 0496909595465696 0000-0002-0886-7798 |
identifier_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016. WOS:000392693000024 0496909595465696 0000-0002-0886-7798 |
url |
http://hdl.handle.net/11449/159329 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
3 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808129350057328640 |