A tunnel-FET device model based on Verilog-A applied to circuit simulation

Detalhes bibliográficos
Autor(a) principal: Rangel, R. S.
Data de Publicação: 2018
Outros Autores: Agopian, P. G.D. [UNESP], Martino, J. A.
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/SBMicro.2018.8511536
http://hdl.handle.net/11449/187117
Resumo: This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.
id UNSP_9fb610ac0c1c95098a4fecf324b64e63
oai_identifier_str oai:repositorio.unesp.br:11449/187117
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling A tunnel-FET device model based on Verilog-A applied to circuit simulationCircuit simulationTFETVerilog AThis work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.LSI/PSI/USP University of Sao PauloCI Brasil Program (CT-SP)Sao Paulo State University (UNESP)Sao Paulo State University (UNESP)Universidade de São Paulo (USP)CI Brasil Program (CT-SP)Universidade Estadual Paulista (Unesp)Rangel, R. S.Agopian, P. G.D. [UNESP]Martino, J. A.2019-10-06T15:25:58Z2019-10-06T15:25:58Z2018-10-26info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1109/SBMicro.2018.851153633rd Symposium on Microelectronics Technology and Devices, SBMicro 2018.http://hdl.handle.net/11449/18711710.1109/SBMicro.2018.85115362-s2.0-8505742795204969095954656960000-0002-0886-7798Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018info:eu-repo/semantics/openAccess2021-10-22T21:54:16Zoai:repositorio.unesp.br:11449/187117Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T13:45:43.575651Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv A tunnel-FET device model based on Verilog-A applied to circuit simulation
title A tunnel-FET device model based on Verilog-A applied to circuit simulation
spellingShingle A tunnel-FET device model based on Verilog-A applied to circuit simulation
Rangel, R. S.
Circuit simulation
TFET
Verilog A
title_short A tunnel-FET device model based on Verilog-A applied to circuit simulation
title_full A tunnel-FET device model based on Verilog-A applied to circuit simulation
title_fullStr A tunnel-FET device model based on Verilog-A applied to circuit simulation
title_full_unstemmed A tunnel-FET device model based on Verilog-A applied to circuit simulation
title_sort A tunnel-FET device model based on Verilog-A applied to circuit simulation
author Rangel, R. S.
author_facet Rangel, R. S.
Agopian, P. G.D. [UNESP]
Martino, J. A.
author_role author
author2 Agopian, P. G.D. [UNESP]
Martino, J. A.
author2_role author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
CI Brasil Program (CT-SP)
Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Rangel, R. S.
Agopian, P. G.D. [UNESP]
Martino, J. A.
dc.subject.por.fl_str_mv Circuit simulation
TFET
Verilog A
topic Circuit simulation
TFET
Verilog A
description This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.
publishDate 2018
dc.date.none.fl_str_mv 2018-10-26
2019-10-06T15:25:58Z
2019-10-06T15:25:58Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/SBMicro.2018.8511536
33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018.
http://hdl.handle.net/11449/187117
10.1109/SBMicro.2018.8511536
2-s2.0-85057427952
0496909595465696
0000-0002-0886-7798
url http://dx.doi.org/10.1109/SBMicro.2018.8511536
http://hdl.handle.net/11449/187117
identifier_str_mv 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018.
10.1109/SBMicro.2018.8511536
2-s2.0-85057427952
0496909595465696
0000-0002-0886-7798
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808128273016684544