A Tunnel-FET device model based on Verilog-A applied to circuit simulation

Detalhes bibliográficos
Autor(a) principal: Rangel, R. S.
Data de Publicação: 2018
Outros Autores: Agopian, P. G. D. [UNESP], Martino, J. A., IEEE
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://hdl.handle.net/11449/184136
Resumo: This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.
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spelling A Tunnel-FET device model based on Verilog-A applied to circuit simulationTFETcircuit simulationverilog AThis work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Univ Sao Paulo, LSI, PSI, Sao Paulo, BrazilCI Brasil Program CT SP, Sao Paulo, BrazilSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, BrazilSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)CI Brasil Program CT SPUniversidade Estadual Paulista (Unesp)Rangel, R. S.Agopian, P. G. D. [UNESP]Martino, J. A.IEEE2019-10-03T18:20:10Z2019-10-03T18:20:10Z2018-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject42018 33rd Symposium On Microelectronics Technology And Devices (sbmicro). New York: Ieee, 4 p., 2018.http://hdl.handle.net/11449/184136WOS:00045119580002704969095954656960000-0002-0886-7798Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2018 33rd Symposium On Microelectronics Technology And Devices (sbmicro)info:eu-repo/semantics/openAccess2021-10-23T02:05:49Zoai:repositorio.unesp.br:11449/184136Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T18:49:29.786701Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv A Tunnel-FET device model based on Verilog-A applied to circuit simulation
title A Tunnel-FET device model based on Verilog-A applied to circuit simulation
spellingShingle A Tunnel-FET device model based on Verilog-A applied to circuit simulation
Rangel, R. S.
TFET
circuit simulation
verilog A
title_short A Tunnel-FET device model based on Verilog-A applied to circuit simulation
title_full A Tunnel-FET device model based on Verilog-A applied to circuit simulation
title_fullStr A Tunnel-FET device model based on Verilog-A applied to circuit simulation
title_full_unstemmed A Tunnel-FET device model based on Verilog-A applied to circuit simulation
title_sort A Tunnel-FET device model based on Verilog-A applied to circuit simulation
author Rangel, R. S.
author_facet Rangel, R. S.
Agopian, P. G. D. [UNESP]
Martino, J. A.
IEEE
author_role author
author2 Agopian, P. G. D. [UNESP]
Martino, J. A.
IEEE
author2_role author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
CI Brasil Program CT SP
Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Rangel, R. S.
Agopian, P. G. D. [UNESP]
Martino, J. A.
IEEE
dc.subject.por.fl_str_mv TFET
circuit simulation
verilog A
topic TFET
circuit simulation
verilog A
description This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.
publishDate 2018
dc.date.none.fl_str_mv 2018-01-01
2019-10-03T18:20:10Z
2019-10-03T18:20:10Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv 2018 33rd Symposium On Microelectronics Technology And Devices (sbmicro). New York: Ieee, 4 p., 2018.
http://hdl.handle.net/11449/184136
WOS:000451195800027
0496909595465696
0000-0002-0886-7798
identifier_str_mv 2018 33rd Symposium On Microelectronics Technology And Devices (sbmicro). New York: Ieee, 4 p., 2018.
WOS:000451195800027
0496909595465696
0000-0002-0886-7798
url http://hdl.handle.net/11449/184136
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2018 33rd Symposium On Microelectronics Technology And Devices (sbmicro)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 4
dc.publisher.none.fl_str_mv Ieee
publisher.none.fl_str_mv Ieee
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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