Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices

Detalhes bibliográficos
Autor(a) principal: Martino, M. D. V.
Data de Publicação: 2017
Outros Autores: Martino, J. A., Agopian, P. G. D. [UNESP], Rooyackers, R., Simoen, E., Collaert, N., Claeys, C., IEEE
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://hdl.handle.net/11449/186355
Resumo: The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (A(d)), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest A(d), FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.
id UNSP_a158fcb58ea238bedaa6c125752212bf
oai_identifier_str oai:repositorio.unesp.br:11449/186355
network_acronym_str UNSP
network_name_str Repositório Institucional da UNESP
repository_id_str 2946
spelling Experimental Analysis of Differential Pairs Designed with Line Tunnel FET DevicesLine TFETPoint TFETFinFETDifferential Pairdifferential gaindimensions mismatchThe aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (A(d)), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest A(d), FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)imec's Logic Device ProgramUniv Sao Paulo, LSI PSI USP, Sao Paulo, BrazilSao Paulo State Univ UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, BrazilImec, Leuven, BelgiumKatholieke Univ Leuven, EE Dept, Leuven, BelgiumSao Paulo State Univ UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, BrazilIeeeUniversidade de São Paulo (USP)Universidade Estadual Paulista (Unesp)ImecKatholieke Univ LeuvenMartino, M. D. V.Martino, J. A.Agopian, P. G. D. [UNESP]Rooyackers, R.Simoen, E.Collaert, N.Claeys, C.IEEE2019-10-04T19:12:24Z2019-10-04T19:12:24Z2017-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject32017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2017.2573-5926http://hdl.handle.net/11449/186355WOS:000463041500024Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s)info:eu-repo/semantics/openAccess2021-10-23T19:02:20Zoai:repositorio.unesp.br:11449/186355Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T21:58:43.158982Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
title Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
spellingShingle Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
Martino, M. D. V.
Line TFET
Point TFET
FinFET
Differential Pair
differential gain
dimensions mismatch
title_short Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
title_full Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
title_fullStr Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
title_full_unstemmed Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
title_sort Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices
author Martino, M. D. V.
author_facet Martino, M. D. V.
Martino, J. A.
Agopian, P. G. D. [UNESP]
Rooyackers, R.
Simoen, E.
Collaert, N.
Claeys, C.
IEEE
author_role author
author2 Martino, J. A.
Agopian, P. G. D. [UNESP]
Rooyackers, R.
Simoen, E.
Collaert, N.
Claeys, C.
IEEE
author2_role author
author
author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
Universidade Estadual Paulista (Unesp)
Imec
Katholieke Univ Leuven
dc.contributor.author.fl_str_mv Martino, M. D. V.
Martino, J. A.
Agopian, P. G. D. [UNESP]
Rooyackers, R.
Simoen, E.
Collaert, N.
Claeys, C.
IEEE
dc.subject.por.fl_str_mv Line TFET
Point TFET
FinFET
Differential Pair
differential gain
dimensions mismatch
topic Line TFET
Point TFET
FinFET
Differential Pair
differential gain
dimensions mismatch
description The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (A(d)), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest A(d), FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.
publishDate 2017
dc.date.none.fl_str_mv 2017-01-01
2019-10-04T19:12:24Z
2019-10-04T19:12:24Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv 2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2017.
2573-5926
http://hdl.handle.net/11449/186355
WOS:000463041500024
identifier_str_mv 2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2017.
2573-5926
WOS:000463041500024
url http://hdl.handle.net/11449/186355
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 3
dc.publisher.none.fl_str_mv Ieee
publisher.none.fl_str_mv Ieee
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
_version_ 1808129380340203520

Registros relacionados