Projeto de célula de memória SRAM em três diferentes nós tecnológicos

• Autor(a) principal: Silva, Pedro Henrique Penna da
• Data de Publicação: 2021
• Tipo de documento: Trabalho de conclusão de curso
• Idioma: por
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://hdl.handle.net/11449/215163
• topic: Semiconductors; Metal oxide semiconductors; Memória de acesso aleatório; Circuitos eletrônicos; Microeletrônica

With a world that is becoming more and more technological, people started to demand more speed and higher performance from electro-electronic devices. Based on this information, the main strategy was to reduce the size of the electronic components to then have a reduction in area, placing more components and thus increasing the complexity of the circuits. Starting in the 1970s, the MOSFET technology revealed itself capable of building ever-smaller transistors, with fast switching and high scaling capacity. Through this miniaturization and the decrease in the occupied area, it was possible to build devices with a larger number of transistors, thus improving their speed and performance. In this work a six-transistor 6TSRAM static random access memory cell was studied, which was designed through Microwind2 software for three different technology nodes: 350 nm, 130 nm and 65 nm. This work was based on comparing the results between the three technology nodes. The first comparison to be made was about the size of the transistors and the total area occupied by the memory cell. The second was about the write and read speed of the cell. The last one was the comparison of the static noise margin. The intention was to show that as the technology node was reduced, there would be a gain in space, speed, and greater susceptibility to noise. This monograph also highlights the problem of decreasing the size of the technology node too much using MOSFET technology, which starts to be influenced by short channel effects