Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process

Detalhes bibliográficos
Autor(a) principal: Oliveira, Vlademir J. S. [UNESP]
Data de Publicação: 2007
Outros Autores: Oki, Nobuo [UNESP]
Tipo de documento: Artigo de conferência
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1109/DTIS.2007.4449491
http://hdl.handle.net/11449/9689
Resumo: An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.
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spelling Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS processAn analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Univ Estadual Paulista, Dept Engn Eletr, Ilha Solteira, BrazilUniv Estadual Paulista, Dept Engn Eletr, Ilha Solteira, BrazilIEEEUniversidade Estadual Paulista (Unesp)Oliveira, Vlademir J. S. [UNESP]Oki, Nobuo [UNESP]2014-05-20T13:28:58Z2014-05-20T13:28:58Z2007-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject52-55http://dx.doi.org/10.1109/DTIS.2007.44494912007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.http://hdl.handle.net/11449/968910.1109/DTIS.2007.4449491WOS:0002562965000101525717947689076Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Erainfo:eu-repo/semantics/openAccess2024-07-04T19:11:55Zoai:repositorio.unesp.br:11449/9689Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T23:22:00.347187Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
title Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
spellingShingle Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
Oliveira, Vlademir J. S. [UNESP]
title_short Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
title_full Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
title_fullStr Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
title_full_unstemmed Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
title_sort Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
author Oliveira, Vlademir J. S. [UNESP]
author_facet Oliveira, Vlademir J. S. [UNESP]
Oki, Nobuo [UNESP]
author_role author
author2 Oki, Nobuo [UNESP]
author2_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (Unesp)
dc.contributor.author.fl_str_mv Oliveira, Vlademir J. S. [UNESP]
Oki, Nobuo [UNESP]
description An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.
publishDate 2007
dc.date.none.fl_str_mv 2007-01-01
2014-05-20T13:28:58Z
2014-05-20T13:28:58Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1109/DTIS.2007.4449491
2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.
http://hdl.handle.net/11449/9689
10.1109/DTIS.2007.4449491
WOS:000256296500010
1525717947689076
url http://dx.doi.org/10.1109/DTIS.2007.4449491
http://hdl.handle.net/11449/9689
identifier_str_mv 2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.
10.1109/DTIS.2007.4449491
WOS:000256296500010
1525717947689076
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 52-55
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv Web of Science
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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