Current mirror designed with GAA nanosheet MOSFETs from room temperature to 200◦C

• Autor(a) principal: Perina, Welder F.
• Data de Publicação: 2021
• Outros Autores: Martino, Joao Antonio, Simoen, Eddy, Veloso, Anabela, Der Agopian, Paula Ghedini [UNESP]
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1088/1361-6641/ac1310; http://hdl.handle.net/11449/222152
• topic: Analog circuit; Current mirror; Lookup table; MOSFET; Nanosheet; Nanowire; Verilog-A

Current mirrors (CMs) are essential building blocks for biasing integrated circuits. The gate-all-around silicon nanosheet MOSFETs (GAA-NS) are excellent candidates for the sub 7 nm technology node. In this work, CMs designed with GAA-NS are studied for the first time. This study is performed from room temperature to 200 ◦C using Verilog-A with Look Up Table based on experimental data of n- and p-type GAA-NS for circuit simulation. The current source (reference current) that supplies the CM is designed with an inverter with feedback for simplicity. Due to the zero temperature coefficient (ZTC) region, multiple designs are made to evaluate each type of biasing (before, after and in the ZTC region). Symmetric and asymmetric VTH for n- and p-type GAA-NS are also analyzed. The asymmetric approach presents a compliance voltage of 0.7 V and 0.8 V, for an n- and p-mirror, respectively, while the symmetric one yields a compliance voltage of 0.75 V for both mirror types, and errors lower than 6%, for the design biasing the transistors before the ZTC region.