Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs
Autor(a) principal: | |
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Data de Publicação: | 2018 |
Outros Autores: | , |
Tipo de documento: | Artigo |
Título da fonte: | Biblioteca Digital de Teses e Dissertações da FEI |
Texto Completo: | https://repositorio.fei.edu.br/handle/FEI/1182 |
Resumo: | © 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain. |
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Biblioteca Digital de Teses e Dissertações da FEI |
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Assalti R.Flandre D.de Souza M.2019-08-19T23:45:17Z2019-08-19T23:45:17Z2018ASSALTI, Rafael; FLANDRE, Denis; de Souza, Michelly. Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 13, n. 2, p. 1-7, 2018.1872-0234https://repositorio.fei.edu.br/handle/FEI/118210.29292/jics.v13i2.15© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.13217Journal of Integrated Circuits and SystemsInfluence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETsinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleAnalog performanceAsymmetric self-cascodeComposite transistorFD SOI nMOSFETinfo:eu-repo/semantics/openAccessreponame:Biblioteca Digital de Teses e Dissertações da FEIinstname:Centro Universitário da Fundação Educacional Inaciana (FEI)instacron:FEI22-s2.0-85062820550https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85062820550&origin=inward2022-06-01FEI/11822022-06-01 03:06:42.59Biblioteca Digital de Teses e Dissertaçõeshttp://sofia.fei.edu.br/pergamum/biblioteca/PRI |
dc.title.none.fl_str_mv |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
title |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
spellingShingle |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs Assalti R. Analog performance Asymmetric self-cascode Composite transistor FD SOI nMOSFET |
title_short |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
title_full |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
title_fullStr |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
title_full_unstemmed |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
title_sort |
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs |
author |
Assalti R. |
author_facet |
Assalti R. Flandre D. de Souza M. |
author_role |
author |
author2 |
Flandre D. de Souza M. |
author2_role |
author author |
dc.contributor.author.fl_str_mv |
Assalti R. Flandre D. de Souza M. |
dc.subject.eng.fl_str_mv |
Analog performance Asymmetric self-cascode Composite transistor FD SOI nMOSFET |
topic |
Analog performance Asymmetric self-cascode Composite transistor FD SOI nMOSFET |
description |
© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain. |
publishDate |
2018 |
dc.date.issued.fl_str_mv |
2018 |
dc.date.accessioned.fl_str_mv |
2019-08-19T23:45:17Z |
dc.date.available.fl_str_mv |
2019-08-19T23:45:17Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.citation.fl_str_mv |
ASSALTI, Rafael; FLANDRE, Denis; de Souza, Michelly. Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 13, n. 2, p. 1-7, 2018. |
dc.identifier.uri.fl_str_mv |
https://repositorio.fei.edu.br/handle/FEI/1182 |
dc.identifier.issn.none.fl_str_mv |
1872-0234 |
dc.identifier.doi.none.fl_str_mv |
10.29292/jics.v13i2.15 |
identifier_str_mv |
ASSALTI, Rafael; FLANDRE, Denis; de Souza, Michelly. Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs. JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), v. 13, n. 2, p. 1-7, 2018. 1872-0234 10.29292/jics.v13i2.15 |
url |
https://repositorio.fei.edu.br/handle/FEI/1182 |
dc.relation.ispartof.none.fl_str_mv |
Journal of Integrated Circuits and Systems |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
reponame:Biblioteca Digital de Teses e Dissertações da FEI instname:Centro Universitário da Fundação Educacional Inaciana (FEI) instacron:FEI |
instname_str |
Centro Universitário da Fundação Educacional Inaciana (FEI) |
instacron_str |
FEI |
institution |
FEI |
reponame_str |
Biblioteca Digital de Teses e Dissertações da FEI |
collection |
Biblioteca Digital de Teses e Dissertações da FEI |
repository.name.fl_str_mv |
|
repository.mail.fl_str_mv |
|
_version_ |
1734750992622157824 |