Parameter extraction, modelling and circuit design for electrolyte-gated transistors on paper

• Autor(a) principal: Bártolo, Nuno Gonçalo Simões
• Data de Publicação: 2018
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10362/56427
• topic: Paper electronics; TFT; EGT; Parameter extraction; Compact model; Verilog- A; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia dos Materiais

Flexible and paper electronics have been getting a lot of attention in the last years. Not only from the scientific community, but also from the end consumer. This ultimately converges in efforts pushing towards the discovery of new and better materials for the TFT technology. With this fast development of new devices, compact models for circuit simulation based on older FETs become obsolete. The availability of fast and accurate models is an essential part of going from single, proof-of-concept devices, to fully operational circuits. In this work, done in the Department of Engineering of the University of Cambridge, the electrical characterization and parameter extraction of state-of-the-art electrolytegated transistors (EGT) on paper substrate, fabricated at UNINOVA/I3N, led to the development of a compact model capable of describing the behaviour of the devices. A detailed overview of the model is provided throughout this work, from the characterization of the device, to simple circuit simulations using a dozen of devices. This, together with the provided Verilog-A code for CAD software implementation, will allow both new and experienced users in circuit design to simulate simple circuits with these EGTs or any other TFT device with similar behaviour with simple tweaks on the model.