Probabilistic approach for yield analysis of dynamic logic circuits
Autor(a) principal: | |
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Data de Publicação: | 2008 |
Outros Autores: | , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UFRGS |
Texto Completo: | http://hdl.handle.net/10183/27616 |
Resumo: | In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 . |
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Brusamarello, LucasSilva, Roberto daWirth, Gilson InacioReis, Ricardo Augusto da Luz2011-01-29T06:00:41Z20081057-7122http://hdl.handle.net/10183/27616000684873In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 .application/pdfengIEEE transactions on circuits and systems. I, Regular Papers. New York. Vol. 55, no. 8 (Sept. 2008), p. 2238-2248MicroeletrônicaDesign for yieldMonte Carlo methodsProbabilistic analysisProcess variabilityVLSIYield estimationProbabilistic approach for yield analysis of dynamic logic circuitsEstrangeiroinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/openAccessreponame:Repositório Institucional da UFRGSinstname:Universidade Federal do Rio Grande do Sul (UFRGS)instacron:UFRGSORIGINAL000684873.pdf000684873.pdfTexto completo (inglês)application/pdf1680583http://www.lume.ufrgs.br/bitstream/10183/27616/1/000684873.pdf84b3cfa4d1cfce6bbc52190612c0bf10MD51TEXT000684873.pdf.txt000684873.pdf.txtExtracted Texttext/plain45591http://www.lume.ufrgs.br/bitstream/10183/27616/2/000684873.pdf.txte606e2dbafbccc89b9ec80732b122437MD52THUMBNAIL000684873.pdf.jpg000684873.pdf.jpgGenerated Thumbnailimage/jpeg2283http://www.lume.ufrgs.br/bitstream/10183/27616/3/000684873.pdf.jpg59d13994b81e6de511d55f0e723a28f6MD5310183/276162021-06-12 04:44:08.328572oai:www.lume.ufrgs.br:10183/27616Repositório de PublicaçõesPUBhttps://lume.ufrgs.br/oai/requestopendoar:2021-06-12T07:44:08Repositório Institucional da UFRGS - Universidade Federal do Rio Grande do Sul (UFRGS)false |
dc.title.pt_BR.fl_str_mv |
Probabilistic approach for yield analysis of dynamic logic circuits |
title |
Probabilistic approach for yield analysis of dynamic logic circuits |
spellingShingle |
Probabilistic approach for yield analysis of dynamic logic circuits Brusamarello, Lucas Microeletrônica Design for yield Monte Carlo methods Probabilistic analysis Process variability VLSI Yield estimation |
title_short |
Probabilistic approach for yield analysis of dynamic logic circuits |
title_full |
Probabilistic approach for yield analysis of dynamic logic circuits |
title_fullStr |
Probabilistic approach for yield analysis of dynamic logic circuits |
title_full_unstemmed |
Probabilistic approach for yield analysis of dynamic logic circuits |
title_sort |
Probabilistic approach for yield analysis of dynamic logic circuits |
author |
Brusamarello, Lucas |
author_facet |
Brusamarello, Lucas Silva, Roberto da Wirth, Gilson Inacio Reis, Ricardo Augusto da Luz |
author_role |
author |
author2 |
Silva, Roberto da Wirth, Gilson Inacio Reis, Ricardo Augusto da Luz |
author2_role |
author author author |
dc.contributor.author.fl_str_mv |
Brusamarello, Lucas Silva, Roberto da Wirth, Gilson Inacio Reis, Ricardo Augusto da Luz |
dc.subject.por.fl_str_mv |
Microeletrônica |
topic |
Microeletrônica Design for yield Monte Carlo methods Probabilistic analysis Process variability VLSI Yield estimation |
dc.subject.eng.fl_str_mv |
Design for yield Monte Carlo methods Probabilistic analysis Process variability VLSI Yield estimation |
description |
In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 . |
publishDate |
2008 |
dc.date.issued.fl_str_mv |
2008 |
dc.date.accessioned.fl_str_mv |
2011-01-29T06:00:41Z |
dc.type.driver.fl_str_mv |
Estrangeiro info:eu-repo/semantics/article |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://hdl.handle.net/10183/27616 |
dc.identifier.issn.pt_BR.fl_str_mv |
1057-7122 |
dc.identifier.nrb.pt_BR.fl_str_mv |
000684873 |
identifier_str_mv |
1057-7122 000684873 |
url |
http://hdl.handle.net/10183/27616 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.ispartof.pt_BR.fl_str_mv |
IEEE transactions on circuits and systems. I, Regular Papers. New York. Vol. 55, no. 8 (Sept. 2008), p. 2238-2248 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
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application/pdf |
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