Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs

Detalhes bibliográficos
Autor(a) principal: de M. Nogueira, Alexandro
Data de Publicação: 2021
Outros Autores: G.D. Agopian, Paula [UNESP], Simoen, Eddy, Rooyackers, Rita, Claeys, Cor, Collaert, Nadine, Martino, Joao A.
Tipo de documento: Artigo
Idioma: eng
Título da fonte: Repositório Institucional da UNESP
Texto Completo: http://dx.doi.org/10.1016/j.sse.2021.108099
http://hdl.handle.net/11449/221971
Resumo: An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered.
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spelling Impact of gate current on the operational transconductance amplifier designed with nanowire TFETsAnalog circuitsGate currentLookup tableNanowireOTASiGeTunnel-FETAn Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered.LSI/PSI/USP University of Sao PauloUNESP Sao Paulo State UniversityImecClaRooE.E. Dept KU LeuvenUNESP Sao Paulo State UniversityUniversidade de São Paulo (USP)Universidade Estadual Paulista (UNESP)ImecClaRooKU Leuvende M. Nogueira, AlexandroG.D. Agopian, Paula [UNESP]Simoen, EddyRooyackers, RitaClaeys, CorCollaert, NadineMartino, Joao A.2022-04-28T19:41:36Z2022-04-28T19:41:36Z2021-12-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://dx.doi.org/10.1016/j.sse.2021.108099Solid-State Electronics, v. 186.0038-1101http://hdl.handle.net/11449/22197110.1016/j.sse.2021.1080992-s2.0-85110383527Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengSolid-State Electronicsinfo:eu-repo/semantics/openAccess2022-04-28T19:41:36Zoai:repositorio.unesp.br:11449/221971Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462022-04-28T19:41:36Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
title Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
spellingShingle Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
de M. Nogueira, Alexandro
Analog circuits
Gate current
Lookup table
Nanowire
OTA
SiGe
Tunnel-FET
title_short Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
title_full Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
title_fullStr Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
title_full_unstemmed Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
title_sort Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
author de M. Nogueira, Alexandro
author_facet de M. Nogueira, Alexandro
G.D. Agopian, Paula [UNESP]
Simoen, Eddy
Rooyackers, Rita
Claeys, Cor
Collaert, Nadine
Martino, Joao A.
author_role author
author2 G.D. Agopian, Paula [UNESP]
Simoen, Eddy
Rooyackers, Rita
Claeys, Cor
Collaert, Nadine
Martino, Joao A.
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Universidade de São Paulo (USP)
Universidade Estadual Paulista (UNESP)
Imec
ClaRoo
KU Leuven
dc.contributor.author.fl_str_mv de M. Nogueira, Alexandro
G.D. Agopian, Paula [UNESP]
Simoen, Eddy
Rooyackers, Rita
Claeys, Cor
Collaert, Nadine
Martino, Joao A.
dc.subject.por.fl_str_mv Analog circuits
Gate current
Lookup table
Nanowire
OTA
SiGe
Tunnel-FET
topic Analog circuits
Gate current
Lookup table
Nanowire
OTA
SiGe
Tunnel-FET
description An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered.
publishDate 2021
dc.date.none.fl_str_mv 2021-12-01
2022-04-28T19:41:36Z
2022-04-28T19:41:36Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/article
format article
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1016/j.sse.2021.108099
Solid-State Electronics, v. 186.
0038-1101
http://hdl.handle.net/11449/221971
10.1016/j.sse.2021.108099
2-s2.0-85110383527
url http://dx.doi.org/10.1016/j.sse.2021.108099
http://hdl.handle.net/11449/221971
identifier_str_mv Solid-State Electronics, v. 186.
0038-1101
10.1016/j.sse.2021.108099
2-s2.0-85110383527
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Solid-State Electronics
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv
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