Nanowire TFET with different Source Compositions applied to Low-Dropout Voltage Regulator

• Autor(a) principal: Do Nascimento Tolêdo, Rodrigo
• Data de Publicação: 2022
• Outros Autores: Martino, Joao Antonio, Der Agopian, Paula Ghedini [UNESP]
• Tipo de documento: Artigo de conferência
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1109/SBMICRO55822.2022.9881035; http://hdl.handle.net/11449/246002
• topic: analog circuit design; low-dropout voltage regulators; LUT; nanowire transistors; TFET

This work presents the analysis of vertical nanowire tunnel field-effect transistors (TFETs) and vertical nanowire MOSFET applied to low-dropout voltage regulator (LDO) design. Three TFETs with sources composed by Si, SiGe an Ge are analyzed. The transistor model is based on lookup tables (LUTs) and are implemented in Verilog-A. In all LDO designs, it was defined a gm/ID of 8 V-1 for the differential amplifier transistors, the load current of 1 μ A and capacitance of 10-pF. A much higher equivalent width was needed for the Si-TFET LDO power transistor which degraded its frequency response, but it consumes an ultra-low quiescent current (300 pA). All TFET based LDOs were stable without the need of a compensator capacitor, while for the MOSFET LDO, a 5-pF capacitor was necessary. The SiGe-TFET LDO presented the higher loop gain (60 dB) which resulted in the best load regulation (0.25mV/μA). The MOSFET LDO presented low efficiency due to high quiescent current, but presented the second-best gain-bandwidth product (GBW) of 52.5 KHz and PSR at low frequency (-49.4 dB). The Ge-TFET LDO presented the best overall results, with the best GBW (70 KHz) and PSR (-52 dB at low frequencies) dissipating only 42.9 nA.