Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis
Autor(a) principal: | |
---|---|
Data de Publicação: | 2023 |
Outros Autores: | , , , , |
Tipo de documento: | Artigo |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1016/j.sse.2023.108611 http://hdl.handle.net/11449/246870 |
Resumo: | This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO. |
id |
UNSP_7320c8fad90937b917ad05ee352674ca |
---|---|
oai_identifier_str |
oai:repositorio.unesp.br:11449/246870 |
network_acronym_str |
UNSP |
network_name_str |
Repositório Institucional da UNESP |
repository_id_str |
2946 |
spelling |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysisAnalog circuit designLine-TFETLow-Dropout Voltage Regulator (LDO)NanowireProcess variabilityTunnel FET (TFET)This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.LSI/PSI/USP University of Sao PauloUNESP Sao Paulo State UniversityUNESP Sao Paulo State UniversityUniversidade de São Paulo (USP)Universidade Estadual Paulista (UNESP)de Lima Silva, Wenitado Nascimento Tolêdo, RodrigoGonçalez Filho, Walterde Moraes Nogueira, AlexandroGhedini Der Agopian, Paula [UNESP]Antonio Martino, Joao2023-07-29T12:52:51Z2023-07-29T12:52:51Z2023-04-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articlehttp://dx.doi.org/10.1016/j.sse.2023.108611Solid-State Electronics, v. 202.0038-1101http://hdl.handle.net/11449/24687010.1016/j.sse.2023.1086112-s2.0-85148545869Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengSolid-State Electronicsinfo:eu-repo/semantics/openAccess2023-07-29T12:52:51Zoai:repositorio.unesp.br:11449/246870Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-05-23T11:47:25.854429Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
title |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
spellingShingle |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis de Lima Silva, Wenita Analog circuit design Line-TFET Low-Dropout Voltage Regulator (LDO) Nanowire Process variability Tunnel FET (TFET) |
title_short |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
title_full |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
title_fullStr |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
title_full_unstemmed |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
title_sort |
Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis |
author |
de Lima Silva, Wenita |
author_facet |
de Lima Silva, Wenita do Nascimento Tolêdo, Rodrigo Gonçalez Filho, Walter de Moraes Nogueira, Alexandro Ghedini Der Agopian, Paula [UNESP] Antonio Martino, Joao |
author_role |
author |
author2 |
do Nascimento Tolêdo, Rodrigo Gonçalez Filho, Walter de Moraes Nogueira, Alexandro Ghedini Der Agopian, Paula [UNESP] Antonio Martino, Joao |
author2_role |
author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) Universidade Estadual Paulista (UNESP) |
dc.contributor.author.fl_str_mv |
de Lima Silva, Wenita do Nascimento Tolêdo, Rodrigo Gonçalez Filho, Walter de Moraes Nogueira, Alexandro Ghedini Der Agopian, Paula [UNESP] Antonio Martino, Joao |
dc.subject.por.fl_str_mv |
Analog circuit design Line-TFET Low-Dropout Voltage Regulator (LDO) Nanowire Process variability Tunnel FET (TFET) |
topic |
Analog circuit design Line-TFET Low-Dropout Voltage Regulator (LDO) Nanowire Process variability Tunnel FET (TFET) |
description |
This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO. |
publishDate |
2023 |
dc.date.none.fl_str_mv |
2023-07-29T12:52:51Z 2023-07-29T12:52:51Z 2023-04-01 |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/article |
format |
article |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1016/j.sse.2023.108611 Solid-State Electronics, v. 202. 0038-1101 http://hdl.handle.net/11449/246870 10.1016/j.sse.2023.108611 2-s2.0-85148545869 |
url |
http://dx.doi.org/10.1016/j.sse.2023.108611 http://hdl.handle.net/11449/246870 |
identifier_str_mv |
Solid-State Electronics, v. 202. 0038-1101 10.1016/j.sse.2023.108611 2-s2.0-85148545869 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Solid-State Electronics |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1803045884012789760 |