Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data

• Autor(a) principal: Tolêdo, Rodrigo do Nascimento
• Data de Publicação: 2022
• Outros Autores: Silva, Wenita de Lima, Gonçalez Filho, Walter, Nogueira, Alexandro de Moraes, Martino, Joao Antonio, Agopian, Paula Ghedini Der [UNESP]
• Tipo de documento: Artigo
• Idioma: eng
• Título da fonte: Repositório Institucional da UNESP
• Texto Completo: http://dx.doi.org/10.1016/j.sse.2022.108328; http://hdl.handle.net/11449/239970
• topic: Analog circuit design; Line-TFET; Low-dropout voltage regulator (LDO); Nanowire; Tunnel FET (TFET)

This paper presents the comparison of Low-Dropout Voltage Regulators (LDOs) designed with Nanowire (NW-TFET) and Line Tunnel FET (Line-TFET), in which the transistors were modeled using Verilog-A and Lookup Tables (LUTs) obtained from experimental data. The LDOs were designed in two gm/ID, load currents and capacitances conditions: 7 V−1, 100 µA, 100 pF and 10.5 V−1, 10 µA, 10 pF. For comparison, a MOSFET LDO was designed with TSCM 0.18 µm PDK. It was observed that both TFET LDOs can be designed without the compensation capacitor to reach stability. The Line-TFET LDO delivers better specifications than the NW-TFET LDO, but with higher current consumption. Comparing with MOSFET LDO, both TFET LDOs present higher efficiency. The Line-TFET LDO showed higher loop gain and lower, but comparable, gain-bandwidth product (GBW) in both biases.