An ASIC for electrical stimulation of adECM/GBM scaffolds

• Autor(a) principal: Leal, Hugo Micael Resende
• Data de Publicação: 2021
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositório Científico de Acesso Aberto de Portugal (Repositórios Cientìficos)
• Texto Completo: http://hdl.handle.net/10773/33728
• topic: ASIC; CMOS; Electrical stimulation; Implantable device; Scaffold; SCI

Spinal Cord Injuries (SCI) have severe consequences such as tetraplegia and paraplegia, which dramatically affect the healthcare of the patients. Successful therapies for such injuries are yet to be attainable. Currently, there is a focus on the study and implementation of small implantable devices that are capable of providing in-vivo electrical stimulation to the spinal cord. Since the impedance of the neural tissue experiences constant changes, the focus is on using current stimulation instead of voltage, to compensate the impedance variations. Furthermore, the usage of scaffolds to provide alignment on the regrown fibers, combined with electrical stimulation is viewed as possible solution for SCI therapy. The NeuroStim- Spinal project, in which this work is inserted, aims to propose a SCI therapy based on in-vivo electrical stimulation combined with 3D printed scaffolds that have in its composition based materials (GBM) and adipose derived decellularized tissue (adECM). The work presented is an application-specific integrated circuit design (ASIC) that provides current-mode stimulation for neuronal regeneration, with the objective of providing in-vivo electrical stimulation for SCI therapy. The main challenges on the design of such devices is in obtaining low circuit area and power consumption, while maintaining the specifications needed. These characteristics are important, since it is intended to be an implantable device. The stimulation circuit consists of, a communication interface with a microcontroller using the Serial Peripheral Communication (SPI) protocol, a 10-bit DAC (Digital-to-Analog Converter) based on a binary charge scaling architecture, a voltage-to-current converter with a feed-forward voltage attenuator (FFVA) architecture, and a H-bridge circuit composed of CMOS switches to drive the scaffold. Results demonstrate that the system developed is capable of driving current from 0 to 200μA with an absolute error bellow 0.75μA. In addition, the developed circuit can provide these range of currents with high linearity to a 15k load impedance. The system can still provide linear stimulation for higher load impedance’s, but in smaller current ranges. Furthermore, the circuit uses a supply voltage of 5V and has an average power dissipation of 19.5mW. The ASIC was developed using a 0.35μm CMOS technology, has dimensions of 270μm per 700μm, which corresponds to a total area of 0.19mm2. The work was developed using the Cadence software.