Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes
Autor(a) principal: | |
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Data de Publicação: | 2016 |
Outros Autores: | , , , , , , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/159327 |
Resumo: | One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm(2)/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current. |
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Repositório Institucional da UNESP |
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Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processesGe pFinFETlong strained devicelow temperature operationSTI firstSTI lastOne of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm(2)/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)FWOLogic IIAP programUniv Sao Paulo, LSI PSI USP, Sao Paulo, BrazilIMEC, Leuven, BelgiumUniv Estadual Paulista, Campus Sao Joao da Boa Vista, Sao Paulo, BrazilKatholieke Univ Leuven, EE Dept, Leuven, BelgiumUniv Estadual Paulista, Campus Sao Joao da Boa Vista, Sao Paulo, BrazilIeeeUniversidade de São Paulo (USP)IMECUniversidade Estadual Paulista (Unesp)Katholieke Univ LeuvenOliveira, Alberto Vinicius deSimoen, EddyAgopian, Paula Ghedini Der [UNESP]Martino, Joao AntonioMitard, JeromeWitters, LiesbethCollaert, NadineThean, AaronClaeys, CorIEEE2018-11-26T15:37:59Z2018-11-26T15:37:59Z2016-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject32016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016.http://hdl.handle.net/11449/159327WOS:00039269300001404969095954656960000-0002-0886-7798Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s)info:eu-repo/semantics/openAccess2021-10-23T21:47:05Zoai:repositorio.unesp.br:11449/159327Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462021-10-23T21:47:05Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
title |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
spellingShingle |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes Oliveira, Alberto Vinicius de Ge pFinFET long strained device low temperature operation STI first STI last |
title_short |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
title_full |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
title_fullStr |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
title_full_unstemmed |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
title_sort |
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes |
author |
Oliveira, Alberto Vinicius de |
author_facet |
Oliveira, Alberto Vinicius de Simoen, Eddy Agopian, Paula Ghedini Der [UNESP] Martino, Joao Antonio Mitard, Jerome Witters, Liesbeth Collaert, Nadine Thean, Aaron Claeys, Cor IEEE |
author_role |
author |
author2 |
Simoen, Eddy Agopian, Paula Ghedini Der [UNESP] Martino, Joao Antonio Mitard, Jerome Witters, Liesbeth Collaert, Nadine Thean, Aaron Claeys, Cor IEEE |
author2_role |
author author author author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) IMEC Universidade Estadual Paulista (Unesp) Katholieke Univ Leuven |
dc.contributor.author.fl_str_mv |
Oliveira, Alberto Vinicius de Simoen, Eddy Agopian, Paula Ghedini Der [UNESP] Martino, Joao Antonio Mitard, Jerome Witters, Liesbeth Collaert, Nadine Thean, Aaron Claeys, Cor IEEE |
dc.subject.por.fl_str_mv |
Ge pFinFET long strained device low temperature operation STI first STI last |
topic |
Ge pFinFET long strained device low temperature operation STI first STI last |
description |
One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm(2)/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current. |
publishDate |
2016 |
dc.date.none.fl_str_mv |
2016-01-01 2018-11-26T15:37:59Z 2018-11-26T15:37:59Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016. http://hdl.handle.net/11449/159327 WOS:000392693000014 0496909595465696 0000-0002-0886-7798 |
identifier_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2016. WOS:000392693000014 0496909595465696 0000-0002-0886-7798 |
url |
http://hdl.handle.net/11449/159327 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2016 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
3 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1803047277457047552 |