Experimental comparison between relaxed and strained Ge pFinFETs
Autor(a) principal: | |
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Data de Publicação: | 2017 |
Outros Autores: | , , , , , , , , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://hdl.handle.net/11449/160099 |
Resumo: | The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices. |
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Repositório Institucional da UNESP |
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Experimental comparison between relaxed and strained Ge pFinFETsFinFETgermaniump-typestrainedrelaxedThe experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)FWOUniv Sao Paulo, LSI PSI EPUSP, Sao Paulo, BrazilUNESP, Sao Joao Da Boa Vista, BrazilImec, Leuven, BelgiumUniv Ghent, Dept Solid St Sci, Ghent, BelgiumKatholieke Univ Leuven, ESAT, EE, Leuven, BelgiumUNESP, Sao Joao Da Boa Vista, BrazilIeeeUniversidade de São Paulo (USP)Universidade Estadual Paulista (Unesp)ImecUniv GhentKatholieke Univ LeuvenOliveira, A. V.Agopian, P. G. D. [UNESP]Martino, J. A.Simoen, E.Mitard, J.Witters, L.Collaert, N.Claeys, C.Sarafis, P.Nassiopoulou, A. G.2018-11-26T15:47:29Z2018-11-26T15:47:29Z2017-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject180-1832017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017.2330-5738http://hdl.handle.net/11449/160099WOS:00042521090004804969095954656960000-0002-0886-7798Web of Sciencereponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPeng2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017)info:eu-repo/semantics/openAccess2021-10-23T21:44:34Zoai:repositorio.unesp.br:11449/160099Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T20:18:56.985297Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
Experimental comparison between relaxed and strained Ge pFinFETs |
title |
Experimental comparison between relaxed and strained Ge pFinFETs |
spellingShingle |
Experimental comparison between relaxed and strained Ge pFinFETs Oliveira, A. V. FinFET germanium p-type strained relaxed |
title_short |
Experimental comparison between relaxed and strained Ge pFinFETs |
title_full |
Experimental comparison between relaxed and strained Ge pFinFETs |
title_fullStr |
Experimental comparison between relaxed and strained Ge pFinFETs |
title_full_unstemmed |
Experimental comparison between relaxed and strained Ge pFinFETs |
title_sort |
Experimental comparison between relaxed and strained Ge pFinFETs |
author |
Oliveira, A. V. |
author_facet |
Oliveira, A. V. Agopian, P. G. D. [UNESP] Martino, J. A. Simoen, E. Mitard, J. Witters, L. Collaert, N. Claeys, C. Sarafis, P. Nassiopoulou, A. G. |
author_role |
author |
author2 |
Agopian, P. G. D. [UNESP] Martino, J. A. Simoen, E. Mitard, J. Witters, L. Collaert, N. Claeys, C. Sarafis, P. Nassiopoulou, A. G. |
author2_role |
author author author author author author author author author |
dc.contributor.none.fl_str_mv |
Universidade de São Paulo (USP) Universidade Estadual Paulista (Unesp) Imec Univ Ghent Katholieke Univ Leuven |
dc.contributor.author.fl_str_mv |
Oliveira, A. V. Agopian, P. G. D. [UNESP] Martino, J. A. Simoen, E. Mitard, J. Witters, L. Collaert, N. Claeys, C. Sarafis, P. Nassiopoulou, A. G. |
dc.subject.por.fl_str_mv |
FinFET germanium p-type strained relaxed |
topic |
FinFET germanium p-type strained relaxed |
description |
The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices. |
publishDate |
2017 |
dc.date.none.fl_str_mv |
2017-01-01 2018-11-26T15:47:29Z 2018-11-26T15:47:29Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017. 2330-5738 http://hdl.handle.net/11449/160099 WOS:000425210900048 0496909595465696 0000-0002-0886-7798 |
identifier_str_mv |
2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017. 2330-5738 WOS:000425210900048 0496909595465696 0000-0002-0886-7798 |
url |
http://hdl.handle.net/11449/160099 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017) |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.format.none.fl_str_mv |
180-183 |
dc.publisher.none.fl_str_mv |
Ieee |
publisher.none.fl_str_mv |
Ieee |
dc.source.none.fl_str_mv |
Web of Science reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808129187480862720 |