FPGA hardware linear regression implementation using fixed-point arithmetic
Autor(a) principal: | |
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Data de Publicação: | 2019 |
Outros Autores: | , |
Tipo de documento: | Artigo de conferência |
Idioma: | eng |
Título da fonte: | Repositório Institucional da UNESP |
Texto Completo: | http://dx.doi.org/10.1145/3338852.3339853 http://hdl.handle.net/11449/198009 |
Resumo: | In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW. |
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Repositório Institucional da UNESP |
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FPGA hardware linear regression implementation using fixed-point arithmeticFixed-point arithmeticFPGAHardwareLinear regressionMachine learningIn this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW.Scholl of Engineering São Paulo State University (UNESP)Department of Electronic and Computer Engineering University of LimerickScholl of Engineering São Paulo State University (UNESP)Universidade Estadual Paulista (Unesp)University of LimerickDe Assis Pedrobon Ferreira, Willian [UNESP]Grout, IanDa Silva, Alexandre César Rodrigues [UNESP]2020-12-12T00:56:29Z2020-12-12T00:56:29Z2019-08-26info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://dx.doi.org/10.1145/3338852.3339853Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019.http://hdl.handle.net/11449/19800910.1145/3338852.33398532-s2.0-85073410567Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengProceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019info:eu-repo/semantics/openAccess2021-10-22T20:48:59Zoai:repositorio.unesp.br:11449/198009Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestopendoar:29462024-08-05T22:07:41.575561Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
dc.title.none.fl_str_mv |
FPGA hardware linear regression implementation using fixed-point arithmetic |
title |
FPGA hardware linear regression implementation using fixed-point arithmetic |
spellingShingle |
FPGA hardware linear regression implementation using fixed-point arithmetic De Assis Pedrobon Ferreira, Willian [UNESP] Fixed-point arithmetic FPGA Hardware Linear regression Machine learning |
title_short |
FPGA hardware linear regression implementation using fixed-point arithmetic |
title_full |
FPGA hardware linear regression implementation using fixed-point arithmetic |
title_fullStr |
FPGA hardware linear regression implementation using fixed-point arithmetic |
title_full_unstemmed |
FPGA hardware linear regression implementation using fixed-point arithmetic |
title_sort |
FPGA hardware linear regression implementation using fixed-point arithmetic |
author |
De Assis Pedrobon Ferreira, Willian [UNESP] |
author_facet |
De Assis Pedrobon Ferreira, Willian [UNESP] Grout, Ian Da Silva, Alexandre César Rodrigues [UNESP] |
author_role |
author |
author2 |
Grout, Ian Da Silva, Alexandre César Rodrigues [UNESP] |
author2_role |
author author |
dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (Unesp) University of Limerick |
dc.contributor.author.fl_str_mv |
De Assis Pedrobon Ferreira, Willian [UNESP] Grout, Ian Da Silva, Alexandre César Rodrigues [UNESP] |
dc.subject.por.fl_str_mv |
Fixed-point arithmetic FPGA Hardware Linear regression Machine learning |
topic |
Fixed-point arithmetic FPGA Hardware Linear regression Machine learning |
description |
In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW. |
publishDate |
2019 |
dc.date.none.fl_str_mv |
2019-08-26 2020-12-12T00:56:29Z 2020-12-12T00:56:29Z |
dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.1145/3338852.3339853 Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019. http://hdl.handle.net/11449/198009 10.1145/3338852.3339853 2-s2.0-85073410567 |
url |
http://dx.doi.org/10.1145/3338852.3339853 http://hdl.handle.net/11449/198009 |
identifier_str_mv |
Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019. 10.1145/3338852.3339853 2-s2.0-85073410567 |
dc.language.iso.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019 |
dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
eu_rights_str_mv |
openAccess |
dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
instname_str |
Universidade Estadual Paulista (UNESP) |
instacron_str |
UNESP |
institution |
UNESP |
reponame_str |
Repositório Institucional da UNESP |
collection |
Repositório Institucional da UNESP |
repository.name.fl_str_mv |
Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
repository.mail.fl_str_mv |
|
_version_ |
1808129394186649600 |